In modern computer systems, demand for memory capacity and bandwidth keeps growing. Recent performance scaling of microprocessors relies on increasing the number of cores per chip, and multi-core and many core chip multi-processors (“CMP”) demand even higher memory bandwidth and capacity through multiple memory controllers per processor. The power budget of main memory modules is similar to or even higher than that of processors in current computer systems.
However, typical memory modules are energy inefficient. For example, too many bits are activated per memory access and most of the bits that are accessed are stored back without being used, wasting dynamic power. By exploiting locality of access patterns, multiple temporally adjacent memory accesses can be combined by either a compiler or memory controller to use more bits per memory activation. But these attempts achieve limited success in applications with irregular access patterns. The efficiency of this approach is restricted by the random nature of memory accesses in general applications and even exacerbated in CMP memory systems, since independent memory access requests from multiple threads are interleaved.
What is desired is a memory system enabling access to information that saves energy without significantly sacrificing system performance.